1. Field of the Invention PA1 2. Related Art
This invention relates generally to a layout arrangement of a microelectronic device in which a plurality of interconnect lines, such as signal wirings for driving a decoder circuit in a memory chip, are arranged in parallel with power supply lines, and more particularly relates to a semiconductor integrated circuit device using two or more layers of interconnect lines.
FIG. 4 shows a layout of a conventional memory chip. Memory chip 1 is a read-only memory (ROM), and is composed of four memory cell blocks 2a to 2d. Between memory cell blocks 2a and 2b are arranged a row decoder circuit 3a including a decoder and a buffer for driving a word line of memory cell block 2a and a row decoder circuit 3b of memory cell block 2b so as to confront each other. Between memory cell blocks 2c and 2d are also arranged respective row decoder circuits 3c and 3d so as to confront each other.
In an upper part of FIG. 4, column decoder circuits 5a to 5d and sense amplifier circuits 6a to 6d for processing signals of bit lines of respective memory cell blocks 2a to 2d are arranged for memory cell blocks 2a to 2d, respectively. In a lower part of FIG. 4, peripheral circuits 4a and 4b including predecoder circuits in which signals for driving the row decoders and so forth are arranged for memory cell blocks 2a to 2d as shown. Peripheral circuit 4a is a circuit common to decoder circuits 3a and 3b, and arranged under memory cell blocks 2a and 2b. Peripheral circuit 4b is a circuit common to decoder circuits 3c and 3d, and arranged under memory cell blocks 2c and 2d .
In the arrangement of power supply wirings for supplying power to these circuits, a pad 7 supplied with Vss (0V) is formed on the outer circumferential side of sense amplifier circuits 6a and 6b. A main wiring 11 is arranged around chip 1 from pad 7, and Vss is applied to respective circuits by branch wirings 12 which are arranged in parallel with respective circuits so as to run towards the center of chip 1 from mother wiring 11. In memory cell blocks 2a to 2d and row decoder circuits 3a to 3d, Vss is supplied to respective cells 2a to 2d and circuits 3a to 3d through branch wirings 13 branched further from a part 12a of branch wirings 12.
A pad 8 supplied with Vdd (5V) is formed on the outer circumferential side of predecoder circuits 4a and 4b. A main wiring 21 is formed from pad 8 in-between memory cell blocks 2b and 2c, and Vdd is supplied to respective circuits through branch wirings 22 arranged in parallel with respective circuits from mother wiring 21 toward the circumference of chip 1. In row decoder circuits 3a to 3d, Vdd is supplied to decoder circuits 3a to 3d through branch wirings 23 branched further from a part 22a of branch wiring 22.
As described above, the power supply lines, Vss and Vdd, are arranged in separated positions so that Vss is supplied from the outer circumference to the center of chip 1 and Vdd is supplied from the center to the outer circumference. By adopting such a layout that wiring channels of Vss and Vdd are separated, wirings of Vss and Vdd avoid intersecting each other.
In chip 1 having such a layout, a region II where signal wirings which connect peripheral circuits 4a and 4b and row decoders 3a to 3d with one another gather together is a region where signal wirings and power supply wirings intersect one another, and is also one of wiring channels having the highest density in chip 1. Thus, the layout of region II is one of the most important factors for determining access speed and chip size of memory chip 1.
FIG. 5 shows a layout of region II in a conventional device. In a common bus region 30 between row decoder circuits 3a and 3b, n lines of signal wirings 31.1 to 31.n from peripheral circuit 4a to decoder circuits 3a and 3b are arranged in parallel with one another while being placed between power supply wirings 23a and 23b. Wirings 31.1 to 31.n are connected with respective jumpers 42.1 to 42.n of n pieces of function cells 41.1 to 41.n of peripheral circuit 4a. The wirings for signals outputted from these jumpers 42.1 to 42.n generally intersect with power supply wiring 12 of peripheral circuit 4a which is laid out along both ends of peripheral circuit 4a. As a result, jumpers 42.1 to 42.n are formed to polycrystalline silicon (poly-Si) across an insulating layer in a lower layer of power supply wiring 12. Further, logic circuits being arranged inside, respective function cells 41.1 to 41.n are arranged in a region having a width wider than the width of common bus 30 where respective signal wirings 31.1 to 31.n are arranged collectively. As a result, respective signal wirings 31.1 to 31.n, connected with jumpers 42.1 to 42.n, arranged in respective function cells 41.1 to 41.n are assembled toward common bus 30 using the portion between row decoder circuits 3a and 3b and peripheral circuit 4a as an assembling region 50.
Signal wirings 31.1 to 31.n, thus assembled, intersect with power supply wiring 22a of row decoders 3a and 3b in a congested region 51 at an inlet portion to common bus 30. Therefore, wiring is made using wirings 32.1 to 32.n in a second layer of highly resistive (relative to metal interconnect) poly-Si formed with an insulating layer put therebetween under power supply wiring 22a in inlet portion 51 of the respective signal wirings 31.1 to 31.n. Wirings 32.1 to 32.n in the second layer and respective signal wirings 31.1 to 31.n are connected with one another through two through holes, a through hole 33 on peripheral circuit 4a side and a via hole 34 on common bus side for every wiring.
In a chip having the above-described layout, some problems related to region II result when memory capacity is increased and high access speed is required. These problems develop when the memory region area is increased along with the memory capacity and the number of signal wiring lines to the decoder, but the size of the chip is limited due to packaging constraints and the like, and it is difficult to widen the width of the common bus. Accordingly, the width of signal wirings is narrowed, and similarly, the wiring width of the second layer of poly-Si is also reduced. Since poly-Si is a high resistance layer, the resistance value of the wiring is increased sharply due to the reduction of the wiring width, and thus resulting in reduction on the access speed to the decoder. Therefore, the access speed to the memory is reduced.
The quantity of through holes for connecting the wirings in the second layer with signal wirings has to be reduced at the same time, and the resistance of this portion is also increased. Therefore, the access speed is reduced further.
Moreover, it is required to form a plurality of through holes in accordance with the number of lines of signal wirings in a limited wiring region as the number of signal wirings is increased. In manufacturing such a region, it is impossible to form all the through holes in perfect shapes, and such defects as via holes having defective connection or high connecting resistance, and via holes short-circuited with adjacent wirings are generated sometimes. Since this percent defective has a tendency to increase as the spacing among via holes gets narrower, the reliability of the memory chip is lowered and the memory of the defective portion cannot be used, thus resulting in reduction in yield. Several means have been proposed as means for solving above-described problems. For example, rather than use poly-Si as an interconnect material in the highly congested areas of interconnection, low resistance metal can be used such as is available in a double or triple metal semiconductor process. However, extra processing steps are required to produce this additional layer of metal interconnect. More particularly, an insulating layer must be formed between two metal layers, and contact holes, or through holes, through the insulating layer must be formed. Additionally, contact resistance which occurs when making connections from one metal layer to the other, must be overcome.
Another proposal is to alter the layout such that power supply wirings do not intersect with signal wirings. In order to avoid interference with the signal wirings, however, it is required to arrange power supply wirings from both sides toward the common bus in a direction perpendicular to the common bus. Namely, the same power supply wiring is to be arranged both at the center and the circumference of the semiconductor device. Such a layout is not applicable to a semiconductor device in which a layout with the power supply wirings separated is adopted in order to avoid mutual intersection of power supply wirings as described previously. Because, in case the layout is adopted, two types of power supplies are arranged at the same time around the semiconductor, and mutual interference between power supply wirings is produced when power is supplied to respective circuits.
Although it is possible to avoid interference by forming the power supply wirings in two layers, the problem of manufacturing process still remains similarly to the previous proposal in which signal wirings are formed in two layers in the upper part. Furthermore, since the channels of feeding lines of the power supply to decoder circuits associated with respective memory cell blocks are different for every power supply wiring, it becomes difficult to set the potential applied to respective circuits to the same level and also to make the signal level identical.